{"repo":"nelsoncsc/verilaxi","free":true,"listed":false,"github":"https://github.com/nelsoncsc/verilaxi","clone":"git clone https://github.com/nelsoncsc/verilaxi.git","description":"SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte-exact real-image round-trip tests. Verilator · Yosys · Docker · CI.","language":"SystemVerilog","stars":23,"topics":["axi4","axi4-lite","axi4-stream","cdc","cdma","dma","fifo","skidbuffer","systemverilog","verification"],"license":"MIT","category":"data-pipelines","readme_excerpt":"verilaxi verilaxi is a lightweight, Verilator-friendly AXI verification library written in SystemVerilog. It provides simple, task-based AXI , AXI-Lite , and AXI-Stream drivers, monitors, and test environments designed for fast RTL bring-up — without UVM. For a deeper walkthrough of the architecture, module inventory, register maps, and verification flow, see the Developer Guide. For the video IP pipeline, both VDMA engines, and the real-image (PNG) round-trip harness, see VIDEO.md. --- ✨ Features - ✅ AXI4, AXI-Lite, and AXI-Stream support - ✅ UART core, AXI-Lite GPIO, and UART↔AXI-Lite control-plane blocks - ✅ AXI DMA, CDMA, and AXI VDMA with triple-buffer frame store and genlock - ✅ AXI-Stream packet, beat, and weighted round-robin arbitration - ✅ AXI-Stream width converters — integer-ratio (k:1 up, 1:k down) and rational-ratio (e.g. 16↔24) - ✅ Synchronous and asynchronous AXI-Stream FIFOs - ✅ Video pipeline: timing generator, colour-bar pattern, video↔AXI-Stream adapters, RGB24 pack/unpack, and capture/display CDC modules - ✅ Verilator-first (tested with FST + Surfer) - ✅ No UVM, no factory, no phases - ✅ Task-based drivers ( write , read , write burst , read burst ) - ✅ Parameterized widths (ADDR, DATA, ID) - ✅ AXI stream backpressure (SRC BP / SINK BP) and AXI slave ready backpressure (READY PROB) - ✅ Selectable test scenarios via TESTTYPE plusarg - ✅ Clean Makefile-driven test selection with interactive menu - ✅ SVA protocol checkers for AXI4-Full, AXI-Lite, and AXI-Str","default_branch":null,"files":null,"tree":[],"storefront":"/r/nelsoncsc","claimed":false,"request_supported":{"post":"https://gitbuyer.com/r/nelsoncsc/verilaxi/request-supported","requests":0},"note":"indexed from public GitHub; nothing is for sale on this page. Clone it from GitHub. Paid listings live at /search."}