{"repo":"krish567366/submicro-execution-engine","free":true,"listed":false,"github":"https://github.com/krish567366/submicro-execution-engine","clone":"git clone https://github.com/krish567366/submicro-execution-engine.git","description":"Sub-microsecond bare-metal execution engine with deterministic replay, lock-free order path, and hardware-timestamped latency measurement.","language":"C++","stars":101,"topics":["algorithmic-trading","backtesting-engine","cpp17","deterministic","educational","hawkes-process","hft","hft-trading","high-frequency-trading","kernal-driver","lock-free","market-making","market-microstructure","market-microstructure-theory","order-book","quantitative-finance","research","simd","ultra-low-latency","zero-copy"],"license":null,"category":"hft_backtesting","readme_excerpt":"<div align=\"center\">\n\n```\n╔═══════════════════════════════════════════════════════════════════════════════╗\n║                                                                               ║\n║        ███████╗██╗   ██╗██████╗ ███╗   ███╗██╗ ██████╗██████╗  ██████╗        ║\n║        ██╔════╝██║   ██║██╔══██╗████╗ ████║██║██╔════╝██╔══██╗██╔═══██╗       ║\n║        ███████╗██║   ██║██████╔╝██╔████╔██║██║██║     ██████╔╝██║   ██║       ║\n║        ╚════██║██║   ██║██╔══██╗██║╚██╔╝██║██║██║     ██╔══██╗██║   ██║       ║\n║        ███████║╚██████╔╝██████╔╝██║ ╚═╝ ██║██║╚██████╗██║  ██║╚██████╔╝       ║\n║        ╚══════╝ ╚═════╝ ╚═════╝ ╚═╝     ╚═╝╚═╝ ╚═════╝╚═╝  ╚═╝ ╚═════╝        ║\n║                                                                               ║\n║            Sub-Microsecond Execution Engine for Algorithmic Trading           ║\n╚═══════════════════════════════════════════════════════════════════════════════╝\n```\n\n<h1>Ultra-Low Latency Trading System</h1>\n\n<p>\n<b>Deterministic, nanosecond-precise execution engine for quantitative trading research</b>\n</p>\n\n[![Build Status](https://img.shields.io/badge/build-passing-brightgreen?style=for-the-badge)](.)\n[![C++17](https://img.shields.io/badge/C%2B%2B-17-blue?style=for-the-badge&logo=cplusplus)](.)\n[![Rust](https://img.shields.io/badge/Rust-1.70%2B-orange?style=for-the-badge&logo=rust)](.)\n[![License](https://img.shields.io/badge/license-Proprietary-red?style=for-the-badge)](LICENSE)\n[![x86-64 Only](https://img.shields.io/badge/Platform-x86--64-critical?style=for-the-badge&logo=intel)](BUILD_REQUIREMENTS.md)\n[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen?style=for-the-badge)](.)\n\n---\n\n## ⚠️ IMPORTANT: Platform Requirements\n\n**This system requires x86-64 architecture (Intel/AMD) with AVX-512 support.**\n\n- ✅ **Linux x86-64**: Full support, < 1μs latency\n- ❌ **ARM64/Apple Silicon**: Not supported (missing AVX-512, TSX, RDTSC)\n- ❌ **Windows**: Not recommended (need PREEMPT_RT kernel)\n\n**📖 See [BUILD_REQUIREMENTS.md](BUILD_REQUIREMENTS.md) for full details**\n\n---\n\n<p>\n<a href=\"https://submicro.krishnabajpai.me/\">Live Demo</a> •\n<a href=\"#key-features\">Features</a> •\n<a href=\"#quick-start\">Quick Start</a> •\n<a href=\"#benchmarks\">Benchmarks</a> •\n<a href=\"#architecture\">Architecture</a> •\n<a href=\"#documentation\">Docs</a>\n</p>\n\n---\n\n### **890ns median latency** | **Deterministic replay** | **Lock-free architecture** | **Research-grade framework**\n\n**[View Interactive Documentation →](https://submicro.krishnabajpai.me/)**\n\n---\n\n> [!TIP]\n> **Branching Strategy**:\n> *   **`main`**: Fundamental execution infrastructure. Primary focus is **Latency Minimization** (median < 900ns) and system determinism.\n> *   **`alpha-optimized`**: Quantitative modeling layer. Primary focus is **Alpha & Signal Optimization** (multi-kernel Hawkes, SIMD features) while keeping latency within sub-microsecond thresholds.\n\n</div>\n\n---\n\n## What Makes This Special?\n\n> **Built for researchers and systems engineers pushing the boundaries of low-latency execution.**\n\nThis isn't just another trading bot. It's a **complete infrastructure** for understanding, measuring, and optimizing execution latency at the **hardware level**.\n\n### The Problem\nTraditional trading systems are black boxes with unpredictable latency, non-deterministic behavior, and poor visibility into where microseconds are lost.\n\n### The Solution\nA **transparent, deterministic execution engine** that:\n- Achieves **sub-microsecond decision latency** (890ns median)\n- Guarantees **bit-identical replay** for audit and debugging\n- Provides **nanosecond-level instrumentation** at every stage\n- Uses **zero-allocation hot paths** and lock-free data structures\n- Simulates **kernel-bypass networking** (DPDK-style)\n- Implements **institutional-grade logging** and monitoring\n\n**Research & Education Only** — Not production-ready. Hardware validation (DPDK/FPGA) is simulated. [Learn more](#hardware-validation--future-work).\n\n**PROPRIETARY LICENSE** — Commercial use prohibited. Written permission required. Contact: krishna@krishnabajpai.me\n\n## Performance Snapshot\n\n<div align=\"center\">\n\n| **Component** | **Median** | **p99** | **p99.9** | \n|------------------|--------------|-----------|--------------|\n| Market Data Ingestion | **87 ns** | 124 ns | 201 ns |\n| Signal Extraction (SIMD) | **40 ns** | 48 ns | 67 ns |\n| Hawkes Update (Power-Law) | **150 ns** | 189 ns | 234 ns |\n| **End-to-End Decision** | **890 ns** | **921 ns** | **1047 ns** |\n| Order Serialization | **34 ns** | 41 ns | 58 ns |\n\n**Measurement Precision:** ±5ns (TSC jitter) | ±17ns (PTP offset)  \n**Test Hardware:** Intel Xeon Platinum 8280 @ 2.7GHz, isolated core, RT kernel\n\n</div>\n\n---\n\n## Key Features\n\n<table>\n<tr>\n<td width=\"50%\">\n\n### **Performance**\n- Sub-microsecond decision latency\n- Zero-copy data paths\n- Lock-free SPSC/MPSC queues\n- Cache-aligned data structures\n- SIMD-optimized computations (AVX-512)\n\n</td>\n<td width=\"50%\">\n\n### **Determinism**\n- Bit-identical replay guarantees\n- Event-driven scheduling\n- Fixed RNG seeds\n- Pre-allocated memory pools\n- TSC-level timestamp precision\n\n</td>\n</tr>\n<tr>\n<td width=\"50%\">\n\n### **Architecture**\n- Kernel-bypass NIC simulation\n- Multivariate Hawkes process\n- Avellaneda-Stoikov market making\n- Adaptive risk management\n- C++/Rust FFI integration\n\n</td>\n<td width=\"50%\">\n\n### **Observability**\n- Real-time metrics dashboard\n- Multi-layer audit logging\n- SHA-256 replay verification\n- Nanosecond-level tracing\n- Latency breakdown analysis\n\n</td>\n</table>\n<br/>\n\n<table>\n<tr>\n<td colspan=\"2\">\n\n### **New: Jitter Profiler & Stall Detection**\n> **\"If you can't measure tail latency, you can't fix it.\"**\nA built-in nanosecond-resolution profiler detects **System Management Interrupts (SMIs)** and scheduler preemption by measuring the cycle-gap between busy-wait iterations. This ensures deep visibility into the \"Zero-Interruption\" guarantee required for p99 latency stability.\n\n</td>\n</tr>\n</table>\n\n---\n\n## Quick Start\n\n**Get running in 60 seconds:**\n\n```bash\n# 1. Clone the repository\ngit clone https://github.com/krish567366/submicro-execution-engine.git\ncd submicro-execution-engine\n\n# 2. Build the system (automatic optimization flags)\n./scripts/build_all.sh\n\n# 3. Run deterministic backtest\nscripts/run_backtest.py\n\n# 4. View results\npython3 scripts/verify_latency.py\nopen dashboard/index.html  # Interactive metrics dashboard\n```\n\n<details>\n<summary><b>Expected Output (click to expand)</b></summary>\n\n```\n=== Low-Latency Trading System ===\nMarket data ingestion: 87ns median\nSignal extraction: 40ns median  \nHawkes update: 150ns median\nDecision latency: 890ns median\n\n--- Cycle: 1000 ---\nMid Price: $100.05\nPosition: 250\nActive Quotes: Bid=100.04 Ask=100.06 Spread=2.00 bps\nHawkes: Buy=12.456 Sell=11.234 Imbalance=0.052\nRegime: NORMAL (multiplier=1.0)\nLast Cycle Latency: 847 ns (0.847 µs)\nDeterminism verified: SHA-256 match\n```\n\n</details>\n\n---\n\n## Architecture Overview\n\n<div align=\"center\">\n\n```\n┌─────────────────────────────────────────────────────────────────────────────┐\n│                         Market Data Feed (Simulated)                         │\n│                    Kernel-Bypass NIC • Zero-Copy DMA Transfer                │\n└───────────────────────────────┬─────────────────────────────────────────────┘\n                                │ 87ns median\n                                ▼\n┌─────────────────────────────────────────────────────────────────────────────┐\n│                    Lock-Free Ring Buffer (SPSC)                              │\n│              Power-of-2 Size • Cache-Line Aligned • No Allocations           │\n└───────────────────────────────┬─────────────────────────────────────────────┘\n                                │ O(1) operations\n                                ▼\n┌─────────────────────────────────────────────────────────────────────────────┐\n│                   Order Book Reconstruction                                  │\n│            Price-Level Aggregation • L2 Depth Tracking                       │\n└───────────────────────────────┬─────────────────────────────────────────────┘\n                                │\n                ┌───────────────┴───────────────┐\n                ▼                               ▼\n┌─────────────────────────────┐   ┌─────────────────────────────────────────┐\n│   Hawkes Process Engine     │   │  Microstructure Features                │\n│   • Self/Cross Excitation   │   │  • Deep OFI (10 levels)                │\n│   • Power-Law Kernel        │   │  • Order Book Imbalance                │\n│   • Buy/Sell Intensity      │   │  • Flow Toxicity (Kyle λ)              │\n└──────────────┬──────────────┘   └──────────────┬──────────────────────────┘\n               │  150ns median                   │ 40ns (SIMD)\n               └───────────────┬─────────────────┘\n                               ▼\n┌─────────────────────────────────────────────────────────────────────────────┐\n│                  FPGA DNN Inference (Simulated)                              │\n│              12 Features → 8 Hidden → 3 Outputs • 400ns Fixed                │\n└───────────────────────────────┬─────────────────────────────────────────────┘\n                                │\n                                ▼\n┌─────────────────────────────────────────────────────────────────────────────┐\n│              Avellaneda-Stoikov Market Making Strategy                       │\n│        HJB Equation • Inventory Skew • Latency-Aware Pricing                 │\n└───────────────────────────────┬─────────────────────────────────────────────┘\n                                │ 890ns E2E\n                                ▼\n┌─────────────────────────────────────────────────────────────────────────────┐\n│                    Risk Control (Pre-Trade + Kill-Switch)                    │\n│          Position Limits • Regime Detection • Atomic Checks                  │\n└───────────────────────────────┬─────────────────────────────────────────────┘\n             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from public GitHub; nothing is for sale on this page. Clone it from GitHub. Paid listings live at /search."}