{"repo":"developeruche/riscv-evm-experiment","free":true,"listed":false,"github":"https://github.com/developeruche/riscv-evm-experiment","clone":"git clone https://github.com/developeruche/riscv-evm-experiment.git","description":"The RISC-V EVM Experiment aims to bridge the gap between the RISC-V instruction set architecture and the Ethereum Virtual Machine (EVM). By integrating RISC-V with the EVM, we seek to create a more efficient, secure, and scalable blockchain VM platform. With the vast target diversity of the RISC-V instruction set architecture.","language":"Rust","stars":11,"topics":["ethereum","evm","riscv","riscv32"],"license":null,"category":"blockchain-web3","readme_excerpt":"RISC-V EVM: A Novel Approach to Blockchain Virtual Machine Architecture Research Project : Exploring the integration of RISC-V instruction set architecture with Ethereum Virtual Machine to create a more versatile blockchain execution environment. Overview This repository contains experimental implementation of a RISC-V based Ethereum Virtual Machine (EVM). The project explores the technical feasibility and performance implications of using the RISC-V instruction set architecture as an alternative execution environment for blockchain smart contracts. By leveraging RISC-V's open architecture, this project aims to enable multi-language smart contract development while investigating potential improvements in execution efficiency and security compared to the traditional stack-based EVM. 🔍 Research Context This implementation serves as the foundation for research exploring whether blockchain platforms could benefit from the advantages of modern CPU architecture while maintaining compatibility with existing smart contract paradigms. Key aspects investigated include: - The feasibility of mapping EVM semantics to RISC-V instructions - Performance characteristics of register-based vs stack-based execution - Developer experience implications for smart contract authors - Technical challenges in preserving EVM security guarantees The complete research paper draft is available here. 🏗️ Project Structure ✨ Key Features - RISC-V Instruction Set : Implementation of the RV32IM subset of RISC","default_branch":null,"files":null,"tree":[],"storefront":"/r/developeruche","claimed":false,"request_supported":{"post":"https://gitbuyer.com/r/developeruche/riscv-evm-experiment/request-supported","requests":0},"note":"indexed from public GitHub; nothing is for sale on this page. Clone it from GitHub. Paid listings live at /search."}