{"repo":"chipsalliance/Surelog","free":true,"listed":false,"github":"https://github.com/chipsalliance/Surelog","clone":"git clone https://github.com/chipsalliance/Surelog.git","description":"SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX","language":"C++","stars":472,"topics":["verilog","parser","python-api","parser-ast","vpi","systemverilog","preprocessor","vpi-api","vpi-standard","antlr"],"license":"Apache-2.0","category":"dev-tools","readme_excerpt":"Surelog SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Goal This project aims at providing a complete SystemVerilog 2017 front-end: a preprocessor, a parser, an elaborator for both design and testbench. We are aiming at supporting all open-source cores. Current status: Surelog's elaboration trees for BlackParrot, Ariane cores are equivalent with Verilator's elaboration tree. Ibex and Earlgrey completely Synthesizes and runs in Hardware with the Surelog/UHDM/Yosys flow. Applications Linter, Simulator, Synthesis tool, Formal tools can use this front-end. They either can be developed as plugins (linked with) or use this front-end as an intermediate step of their compilation flows using the on-disk serialized models (UHDM). Presentation WOSET 2020 UHDM (& Surelog) Paper and Presentation Contributing to this project This project is open to contributions from any users! From the commercial vendor to the Verilog enthusiast, all are welcome. We started maintaining a list of ideas for contribution under Help Wanted Features The preprocessor and the parser use Antlr 4.10 as a parser generator, we track Antlr/main. The preprocessor and the parser ASTs are made persistent on disk using Cap'n'Proto, enabling incremental compilation. The tool is built thread safe and performs multithread parsing. Large files/modules/packages are split for multi-threading compilation. Surelog accepts IEEE Simulator-compliant project","default_branch":null,"files":null,"tree":[],"storefront":"/r/chipsalliance","claimed":false,"request_supported":{"post":"https://gitbuyer.com/r/chipsalliance/Surelog/request-supported","requests":0},"note":"indexed from public GitHub; nothing is for sale on this page. Clone it from GitHub. Paid listings live at /search."}