{"repo":"adilsondias-engineer/fpga-trading-systems","free":true,"listed":false,"github":"https://github.com/adilsondias-engineer/fpga-trading-systems","clone":"git clone https://github.com/adilsondias-engineer/fpga-trading-systems.git","description":"Production-grade low-latency FPGA trading system. Features custom VHDL 10GBASE-R PHY, hardware NASDAQ ITCH 5.0 order book, C++ DPDK/XDP kernel bypass, and PCIe DMA acceleration. LLM-Inference","language":"VHDL","stars":69,"topics":["low-latency","trading-systems","vhdl","cpp","kernel-bypass","market-maker","high-frequency-trading","order-book","dpdk","llm-inference"],"license":"Apache-2.0","category":"trading","readme_excerpt":"Ultra-Low Latency FPGA Trading System & HFT Infrastructure FPGA Trading Systems End-to-end High-Frequency Trading (HFT) infrastructure framework. This repository features a full hardware-software co-design: a custom VHDL 10GBASE-R PHY networking stack running on an FPGA, tightly coupled with an ultra-low latency C++20 kernel bypass subsystem using DPDK and Linux XDP (eBPF). Hardware-accelerated market data processing and order book management for low-latency trading systems. Features custom 10GBASE-R PHY (zero vendor IP) , NASDAQ ITCH 5.0 protocol parsing, hardware order book with sub-microsecond latency, and advanced clock domain crossing architecture. --- Flagship Project: Open-Source 10 Gigabit Ethernet The only open-source custom 10GBASE-R Physical Coding Sublayer for trading systems. Implemented IEEE 802.3ae 10GBASE-R from scratch in VHDL (Projects 33-34, 38): - 64B/66B Encoding - Full block coding implementation - Scrambler/Descrambler - Self-synchronizing polynomial (X^58+X^39+1) - Block Lock FSM - Header-based synchronization state machine - GTX Configuration - 10.3125 Gbps transceiver control - Multi-Protocol Parser - NASDAQ ITCH (UDP) + ASX ITCH (TCP) - Hardware Validated - 30,000+ frames processed, zero vendor IP - Scaling Path: 40GBASE-R4 architecture designed (4× 10G lanes, MLD bonding) - Implementation: Blocked by test equipment cost, ready to implement with hardware access License: Apache 2.0 (free for commercial use) Performance: 50-80ns PHY latency, hardware-","default_branch":null,"files":null,"tree":[],"storefront":"/r/adilsondias-engineer","claimed":false,"request_supported":{"post":"https://gitbuyer.com/r/adilsondias-engineer/fpga-trading-systems/request-supported","requests":0},"note":"indexed from public GitHub; nothing is for sale on this page. Clone it from GitHub. Paid listings live at /search."}