{"repo":"SystemRDL/PeakRDL","free":true,"listed":false,"github":"https://github.com/SystemRDL/PeakRDL","clone":"git clone https://github.com/SystemRDL/PeakRDL.git","description":"Control and status register code generator toolchain","language":"Python","stars":208,"topics":["asic","fpga","eda","registers","register-descriptions","systemrdl-compiler","hardware-description-language","command-line-tool","amba","apb"],"license":"LGPL-3.0","category":"cli-tools","readme_excerpt":"PeakRDL PeakRDL is a free and open-source control & status register (CSR) generator toolchain. This project provides a command-line tool that unifies many aspects of register automation such as generating Verilog CSR RTL, compiling a C register abstraction layer, and many more. PeakRDL is centered around the SystemRDL register description language, but is also capable of working with other CSR specifications like IP-XACT. This tool can: Process SystemRDL 2.0 register descriptions. Generate synthesizable SystemVerilog RTL register blocks. Generate a C register abstraction header for software. Import & export IP-XACT XML. Create rich and dynamic HTML documentation. Build a UVM register model abstraction layer. Extend this tool with your own plugin. ... or use one of the many community plugins Documentation See the PeakRDL Documentation for more details.","default_branch":null,"files":null,"tree":[],"storefront":"/r/SystemRDL","claimed":false,"request_supported":{"post":"https://gitbuyer.com/r/SystemRDL/PeakRDL/request-supported","requests":0},"note":"indexed from public GitHub; nothing is for sale on this page. Clone it from GitHub. Paid listings live at /search."}